This invention relates to apparatus and methods for converting a multi-bit digital input signal into a single-bit sequence, such as a serial stream of pulses.
There are many applications where it is desirable to convert an N-bit signal into an equal-weighted one-bit stream. However, to maintain the accuracy of an N-bit signal, where the signal has a sampling frequency equal to fs, the sampling frequency of the serial one-bit stream should be at least equal to (2N)(fs). Where (2N)(fs) is in the order of several gigahertz, or higher, conventional circuits are not fast enough to provide the needed response.
There are several approaches to the transformation of an N-bit binary number to an equal-weighted sequence of single-bit numbers. A prior art approach for converting an N-bit signal into a serial stream includes the use of a xe2x80x9cthermometer codexe2x80x9d, in which a consecutive series of 1""s are generated equal in number to the total weight of the N-bit number. For example, the 4-bit binary number 1000, which represents the decimal number 8, would be represented by 8 consecutive xe2x80x9c1""sxe2x80x9d, followed by 8 consecutive xe2x80x9c0""sxe2x80x9d, as shown in Table 2, below. If one has a sequence of time frames, each with 8 xe2x80x9c1""sxe2x80x9d and 8 xe2x80x9c0""sxe2x80x9d, passing this sequence through a low-pass analog filter will generate an output proportional to the number 8. However, the strong clustering of 1""s and 0""s requires that the filter cutoff frequency be rather low. Another way of stating this is that the filter cutoff frequency be rather low. Another way of stating this is that the xe2x80x9cquantization noisexe2x80x9d associated with the conversion is predominantly at the frame frequency f. This limits the effective bandwidth of a digital-to-analog converter (DAC) used to convert the digital number into an analog voltage.
Another prior art approach, as shown in FIG. 16, includes a delta-sigma algorithm which relies on accumulators and feedback loops to generate an output sequence. The detailed circuit architecture depends on the order of the modulator and the number of bits. However, it is well known that an input that is xc2xd of full scale (such as the 4-bit number 1000 again) into a basic delta-sigma modulator will generate an output that is an alternating sequence of 1 and 0. This has the same average density as the thermometer code, but the xe2x80x9cquantization noisexe2x80x9d is predominantly at a much higher frequency (8 times the frame frequency), so it is much easier to filter out. More generally, the quantization noise is xe2x80x9cshapedxe2x80x9d in the frequency spectrum, by pushing it up to high frequencies where it can be filtered easily. Delta-sigma modulators can offer outstanding performance, but the circuit architecture is often quite complex and difficult to implement accurately. If not done properly, a delta-sigma modulator can lead to excess noise associated with instabilities or oscillations.
Accordingly, one aspect of Applicants"" invention includes novel apparatus and methods for converting an ordered N-bit (parallel) input signal into a serial stream of one-bit pulses.
Applicants"" invention includes an encoding method for converting an N-bit binary number M to a sequence of 2N single-bit numbers that contains M ones and (2Nxe2x88x92M) zeros. For example, a four-bit binary number 1011 (equivalent to decimal number 11) is converted into a sequence of 24 single-bit numbers: eleven ones and five zeros. Each xe2x80x98onexe2x80x99 in that sequence has equal weight. Such an encoder is not to be confused with a parallel-to-serial converter, which changes an N-bit number to an ordered sequence of N single-bit numbers, from a most significant bit (MSB) to a least significant bit (LSB), to preserve the relative weights of the original binary bits.
In circuits embodying the invention in order to convert a signal represented by an ordered N-bit number into an equivalent serial stream of one bit pulses, there is generated N different sets of pulses or N different sets of frequency signals. [For ease of discussion, sets of pulses will be used for purpose of illustration.] One set of pulses is generated per bit of the N-bit number with each set having a different number of pulses where the number of pulses in each set is a function of the order of the bit to which it corresponds; e.g., corresponding to the first bit or least significant bit (LSB)xe2x80x94one (20) pulse is produced; and corresponding to the Nth bit or most significant bit (MSB)xe2x80x942(Nxe2x88x921) pulses are produced. In a binary system the number of pulses in each set increases by a factor of 2 for each higher order bit starting with the LSB. The pulses of the N sets of pulses may then be combined to form a serial sequence of pulses with contiguous, non-overlapping locations, with the pulses from the set corresponding to the MSB occupying every second location, the pulses from the next lower order bit occupying every fourth location, with the pulses from the sets corresponding to each additional lower order bit occupying one half the number of locations of its higher order bit (e.g., every eighth location, then every sixteenth location, etc.) until the LSB occupies one location.
In one embodiment the N different sets of pulses, corresponding to the bits of an N-bit word, are combined by means of N switches, with each one of the N switches being controlled by a different one of the N bits of the N-bit number. Each switch has a control port to which is applied a different bit of the N-bit number and an input port to which is applied the set of pulses corresponding to the order of the bit applied to that switch. Each switch has an output at which it produces, or reproduces, the value of the signal present at its input port when the value of the bit at its control port is a logic xe2x80x9c1xe2x80x9d. The outputs of the N switches are then combined to produce a serial stream of single-bit pulses corresponding to the value of the N-bit number.
In binary systems, the N bits of the N-bit number are ordered; the first bit, Bit 0, of the N-bit word which is the least significant bit (LSB) and which may also be defined B(0), has a value equal to 20 corresponding to which 1 pulse is generated; the next higher bit of the N-bit word which may be defined as Bit(1), has a value equal to 21 corresponding to which 2 pulses are generated; the Nth bit of the N-bit word which is the most significant bit (MSB) may be defined as B(Nxe2x88x921) and has a value equal to 2(Nxe2x88x921) corresponding to which 2(Nxe2x88x921) pulses are generated. In general, the jth bit of the N-bit word may be defined as B(jxe2x88x921) and has a value equal to 2(jxe2x88x921) corresponding to which 2(jxe2x88x921) pulses are generated; where j varies from 1 for the LSB to N for the MSB. Corresponding to each bit of the N-bit word there is produced a corresponding set of pulses (or sets of frequency signals) proportional to the order of the bit. Thus, in general, for the jth bit of the N-bit word there is produced 2(jxe2x88x921) pulses (or a frequency signal equal to f/2(N+1xe2x88x92j).
The sets of pulses or the frequency signals generated corresponding to each of the N-bit number may be combined by N switches, one switch per bit of the N-bit signal, with each switch having an input port and an output port and a control port to which is applied a different bit of the N-bit word. The different set of pulses are applied to the input port of a switch in correspondence to the order of the bit applied to the control port of the switch. Each switch produces at its output port a set of pulses corresponding to the ones applied to its input when the value of the bit applied to its control port is a logic xe2x80x9c1xe2x80x9d. The outputs of the switches may be combined via an OR circuit and supplied to a common output point at which is produced a serial stream of single-bit pulses having a value corresponding to the N-bit number.
The common output point may be coupled to the input of a shift register whose number of locations (length) is equal to 2N, for further processing and/or storage. The N bits of an N-bit number are assigned and can fill up to 2Nxe2x88x921 locations of the shift register, leaving one blank. In the staggered thermometer algorithm embodying the invention, the Nth bit, MSB or B(Nxe2x88x921), occupies every other location, starting from the second location. The next less significant bit B(Nxe2x88x922) occupies every fourth location, starting from the third location. B(Nxe2x88x92j) occupies every 2j th location, starting with the (1+2jxe2x88x921)th location. Finally, the LSB or B(0) occupies the (1+2Nxe2x88x921)th location.
In many applications where an N-bit signal is converted into a serial one-bit stream of pulses, the conversion is of interest to perform a digital to analog conversion. That is, the one-bit serial stream should be suitable for generating an analog voltage which is an accurate representation of the N-bit signal. Thus, another aspect of the invention includes apparatus and methods for taking a multi-bit digital signal and converting it to an analog signal. Thus, apparatus embodying the invention functions as a digital-to-analog converter or DAC.
Applicants"" invention, which may be referred to as a xe2x80x9cstaggeredxe2x80x9d or xe2x80x9cinterleavedxe2x80x9d thermometer encoder, offers advantages over a delta-sigma encoder approach due its simplicity. In particular, delta-sigma encoders require a feedback algorithm. No such feedback is present or needed in circuits embodying Applicant""s invention. In the xe2x80x9cstaggered thermometer codexe2x80x9d embodying the invention the 1""s are distributed fairly evenly across a frame period, rather than being bunched together at one end, as is the case for a simple thermometer code. This leads to a shaped quantization noise, similar but not identical to that found in a delta-sigma code, which can be efficiently filtered out in a low-pass filter. Furthermore, Applicants"" invention can be implemented using a straightforward circuit architecture, scalable to an arbitrary number of bits.
This is particularly relevant to implementation using high speed superconducting circuits based on Josephson junctions and rapid-single-flux-quantum (RSFQ) digital logic. Applicants have shown that a pattern generator for the xe2x80x9cstaggeredxe2x80x9d thermometer code can be constructed using a set of standard clocked RSFQ cells, including T-flip-flops, splitters, digital delays, and storage registers. Given the extremely high clock speeds and ideal linearity available with RSFQ technology, this architecture is amenable to the development of a highly linear, broadband DAC with many bits of precision. Thus, another aspect of Applicants"" invention includes the use of superconducting circuitry and/or extremely fast semiconductor circuits which can produce the desired response.